This is a working example of a simple FIFO complete with full and empty signals, over flow and under flow protection, implemented in VHDL.
I left the debug signal in to monitor the addr.
The GTKWaveSignals.jpg show the simulated output.
You can get a simple FIFO from here.
Compilation instructions for GHDL and viewing with GKTWave.
Just run the go.bat that is provided.