Written by Ian and Tom on Wednesday 21/02/07
This is a complete VHDL serial solution with test bench and GTKWave signals. You can get it from here.
From the GTKWaveSignals.jpg you can see that bytein is the data being transmitted and byteout is the data received. I have left the debug information in for you to follow what is happening.
When we used the MAX232 chip to covert the FPGA IO pin voltage to RS232 compatible the serial signals are inverted.
So our signals from the MAX232 chip to the FPGA were: default line state high, start bit is low, stop bit goes high.
The signals from the MAX232 to the PC (+12v and -12v) are:
data logic 1=low
data logic 0=high
This means you can drive 0000...1111111110...0000 to send a hex value 0xFF direct from the FPGA into a PC RX pin or if you have a MAX232 level converter in the way, you drive the opposite: 1111...0000000001...1111
Compilation instructions for GHDL and viewing with GKTWave.
ghdl -a simpleSerialRx.vhdl
ghdl -a simpleSerialTx.vhdl
ghdl -a simpleSerialTx_tb.vhdl
ghdl -e simpleSerialTx_tb
ghdl -r simpleSerialTx_tb --vcd= simpleSerialTx.vcd --stop-time=1us
gtkwave simpleSerialTx.vcd signals