Written by Tom on Tuesday 12/12/06
A few years back I had an opportunity to work with FPGA's but first I had to teach myself VHDL.
Step 1. I went to our work library and checked out a book titled "A guide to VHDL"
Why I liked this book: it had ten chapters, I read one a day and in a week and a half had the basics nailed.
You can get it here.
Step 2. After learning a few different programming languages I can never remember syntax so
I found this site helpful Accolade Keyword reference.
Step 3. Get yourself a good editor that is going to help and not hinder,
Xemacs is the only choice very powerful and FREE. Get it here.
Step 4. Basically after a few concepts, you need to understand that VHDL once synthesized is not procedural
but concurrent. With every clock cycle all components will/can do something. This takes some getting used to,
but you can write something like 'C', but with a clock cycle wait between instructions (which you have to put in explicitly).
Also, you need to be careful with data types and converting between them, sometimes it isn't easy.
Step 5. Design strategy. Most programmers love to jump right and code as soon as the problem domain has
been presented to them. Most of the time this produces crappy code. We programmers need a little discipline.
For VHDL if you can draw the wave diagrams then you understand the problem domain and have a good base to begin coding from.
Step 6. Follow the "The Ten Commandments of Excellent Design-VHDL Code Examples" By Peter Chambers.
You can get your own copy here.
Let me add a couple of my own.
11. All asynchronous inputs to the FPGA shall be protected against metastability.
This isn't just a nice to have - it is a real-world design killer that we have seen raise its ugly head many times.
Very difficult to debug too!
12. All components shall have synchronous reset.
13. All signals reset to a defined state (an undefined signal as an input to a block will
propagate through and make all the outputs undefined too after some time).
This does not mean they are declared with a default value, because this
does not always get translated to hardware.. we mean that within the synchronous
reset, all signals are forced to an initialisation state.